Analysis & Synthesis report for top
Wed Jun 20 13:05:57 2012
Quartus II Version 9.0 Build 132 02/25/2009 SJ Full Version
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; Table of Contents ;
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1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Analysis & Synthesis Messages
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; Legal Notice ;
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Copyright (C) 1991-2009 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+--------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-------------------------------+------------------------------------------+
; Analysis & Synthesis Status ; Failed - Wed Jun 20 13:05:57 2012 ;
; Quartus II Version ; 9.0 Build 132 02/25/2009 SJ Full Version ;
; Revision Name ; top ;
; Top-level Entity Name ; top ;
; Family ; Stratix II ;
; Logic utilization ; N/A until Partition Merge ;
; Combinational ALUTs ; N/A until Partition Merge ;
; Dedicated logic registers ; N/A until Partition Merge ;
; Total registers ; N/A until Partition Merge ;
; Total pins ; N/A until Partition Merge ;
; Total virtual pins ; N/A until Partition Merge ;
; Total block memory bits ; N/A until Partition Merge ;
; DSP block 9-bit elements ; N/A until Partition Merge ;
; Total PLLs ; N/A until Partition Merge ;
; Total DLLs ; N/A until Partition Merge ;
+-------------------------------+------------------------------------------+
+----------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+----------------------------------------------------------------+--------------------+--------------------+
; Option ; Setting ; Default Value ;
+----------------------------------------------------------------+--------------------+--------------------+
; Top-level entity name ; top ; top ;
; Family name ; Stratix II ; Stratix II ;
; Use Generated Physical Constraints File ; Off ; ;
; Use smart compilation ; Off ; Off ;
; Restructure Multiplexers ; Auto ; Auto ;
; Create Debugging Nodes for IP Cores ; Off ; Off ;
; Preserve fewer node names ; On ; On ;
; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
; VHDL Version ; VHDL93 ; VHDL93 ;
; State Machine Processing ; Auto ; Auto ;
; Safe State Machine ; Off ; Off ;
; Extract Verilog State Machines ; On ; On ;
; Extract VHDL State Machines ; On ; On ;
; Ignore Verilog initial constructs ; Off ; Off ;
; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
; Parallel Synthesis ; Off ; Off ;
; DSP Block Balancing ; Auto ; Auto ;
; NOT Gate Push-Back ; On ; On ;
; Power-Up Don't Care ; On ; On ;
; Remove Redundant Logic Cells ; Off ; Off ;
; Remove Duplicate Registers ; On ; On ;
; Ignore CARRY Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore LCELL Buffers ; Off ; Off ;
; Ignore SOFT Buffers ; On ; On ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Optimization Technique ; Balanced ; Balanced ;
; Carry Chain Length ; 70 ; 70 ;
; Auto Carry Chains ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
; Auto ROM Replacement ; On ; On ;
; Auto RAM Replacement ; On ; On ;
; Auto DSP Block Replacement ; On ; On ;
; Auto Shift Register Replacement ; Auto ; Auto ;
; Auto Clock Enable Replacement ; On ; On ;
; Strict RAM Replacement ; Off ; Off ;
; Allow Synchronous Control Signals ; On ; On ;
; Force Use of Synchronous Clear Signals ; Off ; Off ;
; Auto RAM Block Balancing ; On ; On ;
; Auto RAM to Logic Cell Conversion ; Off ; Off ;
; Auto Resource Sharing ; Off ; Off ;
; Allow Any RAM Size For Recognition ; Off ; Off ;
; Allow Any ROM Size For Recognition ; Off ; Off ;
; Allow Any Shift Register Size For Recognition ; Off ; Off ;
; Use LogicLock Constraints during Resource Balancing ; On ; On ;
; Ignore translate_off and synthesis_off directives ; Off ; Off ;
; Timing-Driven Synthesis ; Off ; Off ;
; Show Parameter Settings Tables in Synthesis Report ; On ; On ;
; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
; Synchronization Register Chain Length ; 2 ; 2 ;
; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;
; HDL message level ; Level2 ; Level2 ;
; Suppress Register Optimization Related Messages ; Off ; Off ;
; Number of Removed Registers Reported in Synthesis Report ; 100 ; 100 ;
; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
; Clock MUX Protection ; On ; On ;
; Auto Gated Clock Conversion ; Off ; Off ;
; Block Design Naming ; Auto ; Auto ;
; SDC constraint protection ; Off ; Off ;
; Synthesis Effort ; Auto ; Auto ;
; Allows Asynchronous Clear Usage For Shift Register Replacement ; On ; On ;
; Analysis & Synthesis Message Level ; Medium ; Medium ;
+----------------------------------------------------------------+--------------------+--------------------+
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 9.0 Build 132 02/25/2009 SJ Full Version
Info: Processing started: Wed Jun 20 13:05:56 2012
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off top -c top
Info: Found 2 design units, including 1 entities, in source file transmiter.vhd
Info: Found design unit 1: transmiter-behav
Info: Found entity 1: transmiter
Info: Found 2 design units, including 1 entities, in source file fzdiv.vhd
Info: Found design unit 1: fzdiv-behav
Info: Found entity 1: fzdiv
Info: Found 2 design units, including 1 entities, in source file recver.vhd
Info: Found design unit 1: recver-behav
Info: Found entity 1: recver
Info: Found 2 design units, including 1 entities, in source file top.vhd
Info: Found design unit 1: top-sys
Info: Found entity 1: top
Error (10437): VHDL Association List error at top.vhd(50): positional associations must be listed before named associations File: D:/vhdl/vhdl/uart/top/top.vhd Line: 50
Error: Quartus II Analysis & Synthesis was unsuccessful. 1 error, 0 warnings
Error: Peak virtual memory: 186 megabytes
Error: Processing ended: Wed Jun 20 13:05:57 2012
Error: Elapsed time: 00:00:01
Error: Total CPU time (on all processors): 00:00:01
