altera FPGA/CPLD高级篇(VHDL源代码)

						----- ! -------- W A R N I N G -------- ! -----
						----- ! -------- FIR COMPILER GENERATED FILE --- ! -----
						---------------------DO NOT ATTEMPT TO MODIFY! -----
				
				width = 12;
				depth = 8;
				addrex_radix = hex;
				data_radix = hex;
				
				--SET1--;
				--COEF 16 : 508;
				--COEF 17 : 510;
				--COEF 18 : 511;
				content
				  begin
					0	: 0;
					1	: 1fc;
					2	: 1fe;
					3	: 3fa;
					4	: 1ff;
					5	: 3fb;
					6	: 3fd;
					7	: 5f9;
				END;