library ieee;
use ieee.std_logic_arith.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity source is
port(clk:in std_logic:='0';
dataout:out std_logic
);
end;
architecture a of source is
signal data:std_logic_vector(0 to 15);
begin
data process(clk)
variable m:integer range 0 to 15;
variable n:integer range 0 to 15;
begin
if(clk'event and clk='1') then
n:=m mod 16 ;
dataout m:=m+1;
end if;
end process;
end ;
