CPLD开发板VHDL源程序并附上开发板的原理图

				.i 4
				.o 11
				.s 8
				.p 20
				.reset Rst
				.resettype async
				.clock Clk
				.resetstate st0
				.type fdr
				.ilb In0 In1 In2 In3
				.ob Out0 Out1 Out2 Out3 Out4 Out5 Out6 Out7 Out8
				    Out9 Out10
				.obdefault 00000000000
				.ffname state
				.fftype d
				.usedc 0
				.code Auto
				11-- st0 st0 00000000000
				10-- st0 st16 00000000000
				0--- st0 st32 00000000000
				---- st1 st4 00000000000
				---- st4 st512 00000000000
				---- st8 st1 00000000000
				---- st16 st0 00000000000
				---- st32 st8 00000000000
				---- st128 st512 00000000000
				--00 st512 st16 00000000000
				--1- st512 st128 00000000000
				--01 st512 st512 00000000000
				---- st0 void 10000000000
				---- st1 void 00100000000
				---- st4 void 00001000000
				---- st8 void 00000100000
				---- st16 void 00000010000
				---- st32 void 00000001000
				---- st128 void 00000000010
				---- st512 void 01000000000
				.e
				st0	0
				st16	16
				st32	32
				st1	1
				st4	4
				st512	512
				st8	8
				st128	128