Assembler report for div
Sun Jan 11 21:13:06 2009
Version 6.0 Build 178 04/27/2006 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Assembler Summary
3. Assembler Settings
4. Assembler Generated Files
5. Assembler Device Options: E:/Verilog/基础实验/除法器/div.pof
6. Assembler Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+---------------------------------------------------------------+
; Assembler Summary ;
+-----------------------+---------------------------------------+
; Assembler Status ; Successful - Sun Jan 11 21:13:06 2009 ;
; Revision Name ; div ;
; Top-level Entity Name ; div ;
; Family ; MAX II ;
; Device ; EPM240T100C5 ;
+-----------------------+---------------------------------------+
+------------------------------------------------------------------------------------------------------------+
; Assembler Settings ;
+--------------------------------------------------------------------------------+-----------+---------------+
; Option ; Setting ; Default Value ;
+--------------------------------------------------------------------------------+-----------+---------------+
; Use smart compilation ; Off ; Off ;
; Generate Serial Vector Format File (.svf) for Target Device ; Off ; Off ;
; Generate a JEDEC STAPL Format File (.jam) for Target Device ; Off ; Off ;
; Generate an uncompressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off ; Off ;
; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On ; On ;
; In-System Programming Default Clamp State ; Tri-state ; Tri-state ;
; Compression mode ; Off ; Off ;
; Clock source for configuration device ; Internal ; Internal ;
; Clock frequency of the configuration device ; 10 MHZ ; 10 MHz ;
; Divide clock frequency by ; 1 ; 1 ;
; JTAG user code for target device ; Ffffffff ; Ffffffff ;
; Auto user code ; Off ; Off ;
; Security bit ; Off ; Off ;
; Configuration device ; Auto ; Auto ;
; JTAG user code for configuration device ; Ffffffff ; Ffffffff ;
; Configuration device auto user code ; Off ; Off ;
; Generate Tabular Text File (.ttf) For Target Device ; Off ; Off ;
; Generate Raw Binary File (.rbf) For Target Device ; Off ; Off ;
; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off ; Off ;
; Hexadecimal Output File start address ; 0 ; 0 ;
; Hexadecimal Output File count direction ; Up ; Up ;
+--------------------------------------------------------------------------------+-----------+---------------+
+------------------------------------+
; Assembler Generated Files ;
+------------------------------------+
; File Name ;
+------------------------------------+
; E:/Verilog/基础实验/除法器/div.pof ;
+------------------------------------+
+--------------------------------------------------------------+
; Assembler Device Options: E:/Verilog/基础实验/除法器/div.pof ;
+----------------+---------------------------------------------+
; Option ; Setting ;
+----------------+---------------------------------------------+
; Device ; EPM240T100C5 ;
; JTAG usercode ; 0xFFFFFFFF ;
; Checksum ; 0x00190072 ;
+----------------+---------------------------------------------+
+--------------------+
; Assembler Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Assembler
Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
Info: Processing started: Sun Jan 11 21:13:05 2009
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off div -c div
Info: Writing out detailed assembly data for power analysis
Info: Assembler is generating device programming files
Info: Quartus II Assembler was successful. 0 errors, 0 warnings
Info: Processing ended: Sun Jan 11 21:13:06 2009
Info: Elapsed time: 00:00:02
