基于FPGA的UART实现 用VHDL编程

				Analysis & Synthesis Status : Successful - Fri Aug 10 08:20:01 2007
				Quartus II Version : 7.0 Build 33 02/05/2007 SJ Full Version
				Revision Name : UART
				Top-level Entity Name : UART
				Family : Cyclone
				Total logic elements : N/A until Partition Merge
				Total pins : N/A until Partition Merge
				Total virtual pins : N/A until Partition Merge
				Total memory bits : N/A until Partition Merge
				Total PLLs : N/A until Partition Merge