-------------------------------------------------------------------------------
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-- O R E G A N O S Y S T E M S --
-- --
-- Design & Consulting --
-- --
-------------------------------------------------------------------------------
-- --
-- Web: http://www.oregano.at/ --
-- --
-- Contact: 8051@oregano.at --
-- --
-------------------------------------------------------------------------------
-- --
-- MC8051 - VHDL 8051 Microcontroller IP Core --
-- Copyright (C) 2001 OREGANO SYSTEMS --
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file LGPL.TXT. --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
--
--
-- Author: Roland H鰈ler
--
-- Filename: comb_mltplr_rtl.vhd
--
-- Date of Creation: Mon Aug 9 12:14:48 1999
--
-- Version: $Revision: 1.4 $
--
-- Date of Latest Version: $Date: 2002/01/07 12:17:44 $
--
--
-- Description: Multiplier with parameteriseable data width. Realised
-- using combinational logic only.
--
--
--
--
-------------------------------------------------------------------------------
architecture rtl of comb_mltplr is
begin -- rtl
-- purpose: Multiply the multiplicand with the multiplicator.
-- type : combinational
-- inputs : dvdnd_i, dvsor_i
-- outputs: product_o
p_mltply: process (mltplctr_i, mltplcnd_i)
variable v_product : unsigned(DWIDTH*2-1 downto 0);
begin -- process p_divide
v_product := conv_unsigned(unsigned(mltplctr_i)
* unsigned(mltplcnd_i),DWIDTH*2);
product_o
end process p_mltply;
end rtl;
