The following files were generated for 'mc8051_ram' in directory
E:\vtest\xilinx\vhdl8051\mc8051:
mc8051_ram_flist.txt:
Text file listing all of the output files produced when a customized
core was generated in the CORE Generator.
mc8051_ram_readme.txt:
Text file indicating the files generated and how they are used.
mc8051_ram.edn:
Electronic Data Netlist (EDN) file containing the information
required to implement the module in a Xilinx (R) FPGA.
mc8051_ram.vhd:
VHDL wrapper file provided to support functional simulation. This
file contains simulation model customization data that is passed to
a parameterized simulation model for the core.
mc8051_ram.vho:
VHO template file containing code that can be used as a model for
instantiating a CORE Generator module in a VHDL design.
mc8051_ram.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
mc8051_ram.veo:
VEO template file containing code that can be used as a model for
instantiating a CORE Generator module in a Verilog design.
mc8051_ram.asy:
Graphical symbol information file. Used by the ISE tools and some
third party tools to create a symbol representing the core.
mc8051_ram.sym:
Please see the core data sheet.
mc8051_ram.xco:
CORE Generator input file containing the parameters used to
regenerate a core.
Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.
