@N: CD630 :"E:\vtest\xilinx\vhdl8051\mc8051\mc8051_top_.vhd":74:7:74:16|Synthesizing work.mc8051_top.struc
@W: CD638 :"E:\vtest\xilinx\vhdl8051\mc8051\mc8051_top_.vhd":120:9:120:22|Signal s_ramx_data_in is undriven
@N: CD630 :"E:\vtest\xilinx\vhdl8051\mc8051\mc8051_clockdiv.vhd":30:7:30:21|Synthesizing work.mc8051_clockdiv.behavioral
Post processing for work.mc8051_clockdiv.behavioral
@N: CD630 :"E:\vtest\xilinx\vhdl8051\mc8051\mc8051_core_.vhd":75:7:75:17|Synthesizing work.mc8051_core.struc
@W: CD638 :"E:\vtest\xilinx\vhdl8051\mc8051\mc8051_core_struc.vhd":80:9:80:15|Signal s_reset is undriven
@W: CD638 :"E:\vtest\xilinx\vhdl8051\mc8051\mc8051_core_struc.vhd":81:9:81:13|Signal s_clk is undriven
@N: CD630 :"E:\vtest\xilinx\vhdl8051\mc8051\mc8051_tmrctr_.vhd":71:7:71:19|Synthesizing work.mc8051_tmrctr.rtl
Post processing for work.mc8051_tmrctr.rtl
@N: CD630 :"E:\vtest\xilinx\vhdl8051\mc8051\mc8051_siu_.vhd":71:7:71:16|Synthesizing work.mc8051_siu.rtl
Post processing for work.mc8051_siu.rtl
@W: CL170 :"E:\vtest\xilinx\vhdl8051\mc8051\mc8051_siu_rtl.vhd":417:6:417:7|Pruning bit of p_transmit.s_tran_sh_26(10 downto 0) - not in use ...
@N: CD630 :"E:\vtest\xilinx\vhdl8051\mc8051\mc8051_alu_.vhd":75:7:75:16|Synthesizing work.mc8051_alu.struc
@N: CD630 :"E:\vtest\xilinx\vhdl8051\mc8051\dcml_adjust_.vhd":72:7:72:17|Synthesizing work.dcml_adjust.rtl
Post processing for work.dcml_adjust.rtl
@N: CD630 :"E:\vtest\xilinx\vhdl8051\mc8051\comb_divider_.vhd":72:7:72:18|Synthesizing work.comb_divider.rtl
Post processing for work.comb_divider.rtl
@N: CD630 :"E:\vtest\xilinx\vhdl8051\mc8051\comb_mltplr_.vhd":72:7:72:17|Synthesizing work.comb_mltplr.rtl
Post processing for work.comb_mltplr.rtl
@N: CD630 :"E:\vtest\xilinx\vhdl8051\mc8051\addsub_core_.vhd":76:7:76:17|Synthesizing work.addsub_core.struc
@W: CD638 :"E:\vtest\xilinx\vhdl8051\mc8051\addsub_core_struc.vhd":71:9:71:12|Signal s_cy_3 is undriven
@N: CD630 :"E:\vtest\xilinx\vhdl8051\mc8051\addsub_ovcy_.vhd":72:7:72:17|Synthesizing work.addsub_ovcy.rtl
Post processing for work.addsub_ovcy.rtl
@N: CD630 :"E:\vtest\xilinx\vhdl8051\mc8051\addsub_cy_.vhd":72:7:72:15|Synthesizing work.addsub_cy.rtl
Post processing for work.addsub_cy.rtl
Post processing for work.addsub_core.struc
@W: CL162 :"E:\vtest\xilinx\vhdl8051\mc8051\addsub_core_struc.vhd":71:9:71:12|s_cy_3 is not assigned a value (floating)
@N: CD630 :"E:\vtest\xilinx\vhdl8051\mc8051\alucore_.vhd":73:7:73:13|Synthesizing work.alucore.rtl
Post processing for work.alucore.rtl
@N: CD630 :"E:\vtest\xilinx\vhdl8051\mc8051\alumux_.vhd":74:7:74:12|Synthesizing work.alumux.rtl
Post processing for work.alumux.rtl
Post processing for work.mc8051_alu.struc
@N: CD630 :"E:\vtest\xilinx\vhdl8051\mc8051\mc8051_control_.vhd":74:7:74:20|Synthesizing work.mc8051_control.struc
@N: CD231 :"E:\vtest\xilinx\vhdl8051\mc8051\mc8051_p.vhd":259:15:259:16|Using onehot encoding for type t_state (startup="10000")
@N: CD630 :"E:\vtest\xilinx\vhdl8051\mc8051\control_mem_.vhd":75:7:75:17|Synthesizing work.control_mem.rtl
@N: CD231 :"E:\vtest\xilinx\vhdl8051\mc8051\mc8051_p.vhd":259:15:259:16|Using onehot encoding for type t_state (startup="10000")
@W: CD604 :"E:\vtest\xilinx\vhdl8051\mc8051\control_mem_rtl.vhd":663:6:663:19|OTHERS clause is not synthesized
Post processing for work.control_mem.rtl
@N: CD630 :"E:\vtest\xilinx\vhdl8051\mc8051\control_fsm_.vhd":74:7:74:17|Synthesizing work.control_fsm.rtl
@N: CD231 :"E:\vtest\xilinx\vhdl8051\mc8051\mc8051_p.vhd":259:15:259:16|Using onehot encoding for type t_state (startup="10000")
@N: CD232 :"E:\vtest\xilinx\vhdl8051\mc8051\mc8051_p.vhd":265:24:265:25|Using gray code encoding for type t_instr_category
@W: CD604 :"E:\vtest\xilinx\vhdl8051\mc8051\control_fsm_rtl.vhd":2150:10:2150:23|OTHERS clause is not synthesized
Post processing for work.control_fsm.rtl
Post processing for work.mc8051_control.struc
Post processing for work.mc8051_core.struc
Post processing for work.mc8051_top.struc
@W: CL163 :"E:\vtest\xilinx\vhdl8051\mc8051\mc8051_top_.vhd":120:9:120:22|Bit of signal s_ramx_data_in is floating
@W: CL163 :"E:\vtest\xilinx\vhdl8051\mc8051\mc8051_top_.vhd":120:9:120:22|Bit of signal s_ramx_data_in is floating
@W: CL163 :"E:\vtest\xilinx\vhdl8051\mc8051\mc8051_top_.vhd":120:9:120:22|Bit of signal s_ramx_data_in is floating
@W: CL163 :"E:\vtest\xilinx\vhdl8051\mc8051\mc8051_top_.vhd":120:9:120:22|Bit of signal s_ramx_data_in is floating
@W: CL163 :"E:\vtest\xilinx\vhdl8051\mc8051\mc8051_top_.vhd":120:9:120:22|Bit of signal s_ramx_data_in is floating
@W: CL163 :"E:\vtest\xilinx\vhdl8051\mc8051\mc8051_top_.vhd":120:9:120:22|Bit of signal s_ramx_data_in is floating
@W: CL163 :"E:\vtest\xilinx\vhdl8051\mc8051\mc8051_top_.vhd":120:9:120:22|Bit of signal s_ramx_data_in is floating
@W: CL163 :"E:\vtest\xilinx\vhdl8051\mc8051\mc8051_top_.vhd":120:9:120:22|Bit of signal s_ramx_data_in is floating
@W: CL165 :"E:\vtest\xilinx\vhdl8051\mc8051\mc8051_top_.vhd":130:2:130:14|Bit of input datax_i of instance i_mc8051_core is floating
@W: CL165 :"E:\vtest\xilinx\vhdl8051\mc8051\mc8051_top_.vhd":130:2:130:14|Bit of input datax_i of instance i_mc8051_core is floating
@W: CL165 :"E:\vtest\xilinx\vhdl8051\mc8051\mc8051_top_.vhd":130:2:130:14|Bit of input datax_i of instance i_mc8051_core is floating
@W: CL165 :"E:\vtest\xilinx\vhdl8051\mc8051\mc8051_top_.vhd":130:2:130:14|Bit of input datax_i of instance i_mc8051_core is floating
@W: CL165 :"E:\vtest\xilinx\vhdl8051\mc8051\mc8051_top_.vhd":130:2:130:14|Bit of input datax_i of instance i_mc8051_core is floating
@W: CL165 :"E:\vtest\xilinx\vhdl8051\mc8051\mc8051_top_.vhd":130:2:130:14|Bit of input datax_i of instance i_mc8051_core is floating
@W: CL165 :"E:\vtest\xilinx\vhdl8051\mc8051\mc8051_top_.vhd":130:2:130:14|Bit of input datax_i of instance i_mc8051_core is floating
@W: CL165 :"E:\vtest\xilinx\vhdl8051\mc8051\mc8051_top_.vhd":130:2:130:14|Bit of input datax_i of instance i_mc8051_core is floating
@W: CL209 :"E:\vtest\xilinx\vhdl8051\mc8051\control_fsm_.vhd":93:8:93:10|Input port bit of psw(7 downto 0) is unused
@W: CL234 :"E:\vtest\xilinx\vhdl8051\mc8051\control_fsm_.vhd":94:8:94:9|Input port bits of ie(7 downto 0) are unused
@W: CL234 :"E:\vtest\xilinx\vhdl8051\mc8051\control_fsm_.vhd":95:8:95:9|Input port bits of ip(7 downto 0) are unused
@N: CL134 :"E:\vtest\xilinx\vhdl8051\mc8051\control_mem_rtl.vhd":864:4:864:5|Found RAM s_r0, depth=8, width=8
