`timescale 1ns/100ps
module sdram_top(
//input from sys
clk,
rst_n,
read_req,
write_req,
burst_len,
sys_addr,
data_from_sys,
//output to sys
read_ack,
write_ack,
r_data_valid,
w_data_valid,
data_to_sys,
setup_done,
//sdram interface signal
sdr_CKE, // sdr clock enable
sdr_CSn, // sdr chip select
sdr_RASn, // sdr row address
sdr_CASn, // sdr column select
sdr_WEn, // sdr write enable
sdr_BA, // sdr bank address
sdr_DMQ, // sdr dmq
sdr_DATA, // sdr data
sdr_ADDR // sdr address
);
//--------------------------------------------------------
//input from user interface
input clk;
input rst_n;
input read_req;
input write_req;
input[8:0] burst_len;
input[21:0] sys_addr;
input[15:0] data_from_sys;
//output to user interface
output read_ack;
output write_ack; output r_data_valid;
output w_data_valid;
output[15:0] data_to_sys;
output setup_done;
//output to sdarm hardware
output sdr_CKE;
output sdr_CSn;
output sdr_RASn;
output sdr_CASn;
output sdr_WEn;
output[1:0] sdr_BA;
output[1:0] sdr_DMQ;
inout [15:0] sdr_DATA;
output[11:0] sdr_ADDR;
//internal signal
wire init_done;
wire refresh_req;
wire refresh_ack;
wire[2:0] i_state;
wire[3:0] c_state;
//------------------------------------------------------------------------------
main_fsm U0(
.clk(clk),
.rst_n(rst_n),
.read_req(read_req),
.write_req(write_req),
.burst_len(burst_len),
.refresh_req(refresh_req),
.init_done(init_done),
//output
.read_ack(read_ack),
.write_ack(write_ack),
.refresh_ack(refresh_ack),
.r_data_valid(r_data_valid),
.w_data_valid(w_data_valid),
.c_state(c_state)
);
init_fsm U1(
.clk(clk),
.rst_n(rst_n),
.init_done(init_done),
.i_state(i_state)
);
refresh U2(
.clk(clk),
.rst_n(rst_n),
.init_done(init_done),
.refresh_ack(refresh_ack),
.refresh_req(refresh_req)
);
sdr_sig U3(
.clk(clk),
.rst_n(rst_n),
.i_state(i_state),
.c_state(c_state),
.sys_addr(sys_addr),
//output
.sdr_CKE(sdr_CKE), // sdr clock enable
.sdr_CSn(sdr_CSn), // sdr chip select
.sdr_RASn(sdr_RASn), // sdr row address
.sdr_CASn(sdr_CASn), // sdr column select
.sdr_WEn(sdr_WEn), // sdr write enable
.sdr_BA(sdr_BA), // sdr bank address
.sdr_DMQ(sdr_DMQ), // sdr dmq
.sdr_ADDR(sdr_ADDR) // sdr address
);
//-------------------data path handle--------------------------------
assign sdr_DATA =(write_req)?data_from_sys:16'hzzzz; //send data to sdram(write_req)
//assign data_to_sys =(read_req)?sdr_DATA:16'hzzzz; //read data from sdram(read_req)
assign data_to_sys =sdr_DATA;
assign setup_done =init_done;//注意这里：由于init_done驱动的模块比较多，如果不设置为全局信号，后仿真要出问题
endmodule
