.mmregs
STACK .usect "STACK",10h
DecodeDP .usect "Decode",0
TempBufD0 .usect "Decode",1
TempBufD1 .usect "Decode",1
CRAM1 .usect "Decode",1
CRAM2 .usect "Decode",1
BIT_FLGS .usect "Decode",1
OutBitFlag .usect "Decode",1
DeCodedBit .usect "Decode",1
OptimalState .usect "Decode",1
WAT_RD0 .usect "Decode",1
WAT_RD1 .usect "Decode",1
WAT_B0 .usect "Decode",4
WAT_B1 .usect "Decode",4
DAT_B0 .usect "Decode",16
DAT_B1 .usect "Decode",16
.def start
start: STM #BIT_FLGS,AR2
ST #0,*AR2
STM #OutBitFlag,AR2
ST #0,*AR2
LD #-300H,A
STM #WAT_B0,AR2
ST #0,*AR2+
RPT #2
STL A, *AR2+
con_decode
STM #STACK+10h,SP
LD #DecodeDP,DP
CALL BranchWeight
LD BIT_FLGS ,A
AND #1B,A
BC hop_tree_bb,ANEQ
CALL tree_aa_m00
B decode_out
hop_tree_bb
CALL tree_bb_m00
decode_out
CMPM OutBitFlag ,#1
BC decode_end,NTC
ST #0, OutBitFlag
decode_end
B con_decode
BranchWeight:
STM #WAT_RD0,AR1
LD CRAM1,A
ADD CRAM2,A
STL A,*AR1+
LD CRAM1,B
SUB CRAM2,B
STL B,*AR1+
RET
tree_aa_m00
STM #WAT_B0 ,AR1
STM #WAT_B0+2,AR2
STM #WAT_B1,AR3
STM #DAT_B0,AR4
STM #DAT_B0+2*2,AR5
STM #DAT_B1,AR6
STM #1,BRC
STM #02H,AR0
STM #WAT_RD0,AR7
RPTB tre_da_m05-1
LD *AR7+,T
LD *AR1+,A
STL A,TempBufD0
LD *AR2+,A
STL A,TempBufD1
SSBX 1,7
DADST TempBufD0,A
NOP
CMPS A,*AR3+
BC tre_da_m01,NTC
LD *AR5+,16,A
ADDS *AR5+,A
MAR *AR5-0
B tre_da_m02
tre_da_m01
LD *AR4+,16,A
ADDS *AR4+,A
MAR *AR4-0
tre_da_m02
RSBX C
ROR A
STH A,*AR6+
STL A,*AR6+
DSADT TempBufD0,A
NOP
CMPS A,*AR3+
BC tre_da_m03,NTc
LD *AR5+,16,A
ADDS *AR5+,A
MAR *AR4+0
B tre_da_m04
tre_da_m03
LD *AR4+,16,A
ADDS *AR4+,A
MAR *AR5+0
tre_da_m04
SSBX C
ROR A
STH A,*AR6+
STL A,*AR6+
tre_da_m05
ADDM #1, BIT_FLGS
LD BIT_FLGS ,A
SUB #32,A
BC tree_aa_end,ALT
ST #1,OutBitFlag
STM #WAT_B1,AR1
ST #0,OptimalState
ST #0,CRAM2
LD *AR1+,A
STL A,CRAM1
STM #2,BRC
RPTB WAT_B1Max-1
LD *AR1+,16,A
ADDS CRAM1,A
ADDM #1,CRAM2
BC WAT_B1MaxNo ,TC
LD CRAM2,A
STL A,OptimalState
WAT_B1MaxNo:
NOP
WAT_B1Max:
LD #7000,B
SUB CRAM1,B
BC MiniB1_end,BGT
LD CRAM1,B
NEG B
STM #WAT_B1,AR2
STM #3,BRC
RPTB MiniB1_end-1
ADD *AR2,B,A
STL A,*AR2+
MiniB1_end
LD OptimalState ,A
SFTA A ,1
ADD #DAT_B1,A
ADD #1,A
STLM A,AR3
NOP
NOP
LD *AR3,A
ROR A
STM #DeCodedBit,AR2
ST #0,*AR2
BC tree_aa_end, NC
ST #1,*AR2
tree_aa_end
RET
tree_bb_m00
STM #WAT_B1,AR1
STM #WAT_B1+2,AR2
STM #WAT_B0,AR3
STM #DAT_B1,AR4
STM #DAT_B1+2*2,AR5
STM #DAT_B0,AR6
STM #1,BRC
STM #02H,AR0
STM #WAT_RD0,AR7
RPTB tre_db_m05-1
LD *AR7+,T
LD *AR1+,A
STL A,TempBufD0
LD *AR2+,A
STL A,TempBufD1
SSBX 1,7
DADST TempBufD0,A
NOP
CMPS A,*AR3+
BC tre_db_m01,NTC
LD *AR5+,16,A
ADDS *AR5+,A
MAR *AR5-0
B tre_db_m02
tre_db_m01
LD *AR4+,16,A
ADDS *AR4+,A
MAR *AR4-0
tre_db_m02
RSBX C
ROR A
STH A,*AR6+
STL A,*AR6+
DSADT TempBufD0,A
NOP
CMPS A,*AR3+
BC tre_db_m03,NTC
LD *AR5+,16,A
ADDS *AR5+,A
MAR *AR4+0
B tre_db_m04
tre_db_m03
LD *AR4+,16,A
ADDS *AR4+,A
MAR *AR5+0
tre_db_m04
SSBX C
ROR A
STH A,*AR6+
STL A,*AR6+
tre_db_m05
ADDM #1, BIT_FLGS
LD BIT_FLGS ,A
SUB #32,A
BC tree_bb_end,ALT
ST #1,OutBitFlag
STM #WAT_B0,AR1
ST #0,OptimalState
ST #0,CRAM2
LD *AR1+,A
STL A,CRAM1
STM #2,BRC
RPTB WAT_B0Max-1
LD *AR1+,16,A
ADDS CRAM1,A
ADDM #1,CRAM2
BC WAT_B0MaxNo ,TC
LD CRAM2,A
STL A,OptimalState
WAT_B0MaxNo:
NOP
WAT_B0Max:
LD #7000,B
SUB CRAM1,B
BC MiniB0_end,BGT
LD CRAM1,B
STM #WAT_B0,AR2
STM #3,BRC
RPTB MiniB0_end-1
ADD *AR2,B,A
STL A,*AR2+
MiniB0_end
LD OptimalState ,A
SFTA A ,1
ADD #DAT_B0,A
ADD #1,A
STLM A,AR3
NOP
NOP
LD *AR3,A
ROR A
STM #DeCodedBit,AR2
ST #0,*AR2
BC tree_bb_end, NC
ST #1,*AR2
tree_bb_end
RET
.end
