dp_xiliux 的 CPLD Verilog设计实验,串口演示.代码测试通过.

				set _rspFileHandle [open _cpldfit.rsp w]
				puts $_rspFileHandle "-p xc95108-7-PC84"
				puts $_rspFileHandle "-optimize speed"
				puts $_rspFileHandle "-loc on"
				puts $_rspFileHandle "-slew fast"
				puts $_rspFileHandle "-init low"
				if {[string compare "Template Controlled" "Template Controlled"]==0} {
				puts $_rspFileHandle "-pterms 25" } else {
				puts $_rspFileHandle "-pterms Template Controlled" }
				puts $_rspFileHandle "-power std"
				if {1} {
				puts $_rspFileHandle "-localfbk"
				}
				if {1} {
				puts $_rspFileHandle "-pinfbk"
				}
				puts $_rspFileHandle "-inputs 36"
				close $_rspFileHandle
				set _ErrorCode [catch {exec cpldfit -f _cpldfit.rsp receive.ngd} _Results]
				exeputs $_Results
				exit $_ErrorCode