一百多个例子很好的verilog 学习资料

				module binarytogray (clk, reset, binary_input, gray_output);
				input          clk, reset;
				input   [3:0]  binary_input;
				output         gray_output;
				reg     [3:0]  gray_output;
				
				always @ (posedge clk or posedge reset)
				if (reset)
				   begin
				   gray_output 				   end
				else begin
				     gray_output[3] 				     gray_output[2] 				     gray_output[1] 				     gray_output[0] 				     end
				endmodule