//////////////////////////////////////////////////////////////////////
//// ////
//// eth_defines.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/cores/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor (igorM@opencores.org) ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: eth_defines.v,v $
// Revision 1.6 2001/12/05 15:00:16 mohor
// RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors
// instead of the number of RX descriptors).
//
// Revision 1.5 2001/12/05 10:21:37 mohor
// ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead.
//
// Revision 1.4 2001/11/13 14:23:56 mohor
// Generic memory model is used. Defines are changed for the same reason.
//
// Revision 1.3 2001/10/18 12:07:11 mohor
// Status signals changed, Adress decoding changed, interrupt controller
// added.
//
// Revision 1.2 2001/09/24 15:02:56 mohor
// Defines changed (All precede with ETH_). Small changes because some
// tools generate warnings when two operands are together. Synchronization
// between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
// demands).
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
//
//
//
//
//`define WISHBONE_DMA // Using DMA
// Selection of the used memory
//`define XILINX_RAMB4 // Core is going to be implemented in Virtex FPGA and contains Virtex
// specific elements.
//`define ARTISAN_SDP // Core is going to be implemented in ASIC (using Artisan RAM)
`define ETH_MODER_ADR 6'h0 // 0x0
`define ETH_INT_SOURCE_ADR 6'h1 // 0x4
`define ETH_INT_MASK_ADR 6'h2 // 0x8
`define ETH_IPGT_ADR 6'h3 // 0xC
`define ETH_IPGR1_ADR 6'h4 // 0x10
`define ETH_IPGR2_ADR 6'h5 // 0x14
`define ETH_PACKETLEN_ADR 6'h6 // 0x18
`define ETH_COLLCONF_ADR 6'h7 // 0x1C
`define ETH_TX_BD_NUM_ADR 6'h8 // 0x20
`define ETH_CTRLMODER_ADR 6'h9 // 0x24
`define ETH_MIIMODER_ADR 6'hA // 0x28
`define ETH_MIICOMMAND_ADR 6'hB // 0x2C
`define ETH_MIIADDRESS_ADR 6'hC // 0x30
`define ETH_MIITX_DATA_ADR 6'hD // 0x34
`define ETH_MIIRX_DATA_ADR 6'hE // 0x38
`define ETH_MIISTATUS_ADR 6'hF // 0x3C
`define ETH_MAC_ADDR0_ADR 6'h10 // 0x40
`define ETH_MAC_ADDR1_ADR 6'h11 // 0x44
`define ETH_MODER_DEF 32'h0000A000
`define ETH_INT_SOURCE_DEF 32'h00000000
`define ETH_INT_MASK_DEF 32'h00000000
`define ETH_IPGT_DEF 32'h00000012
`define ETH_IPGR1_DEF 32'h0000000C
`define ETH_IPGR2_DEF 32'h00000012
`define ETH_PACKETLEN_DEF 32'h003C0600
`define ETH_COLLCONF_DEF 32'h000F0040
`define ETH_CTRLMODER_DEF 32'h00000000
`define ETH_MIIMODER_DEF 32'h00000064
`define ETH_MIICOMMAND_DEF 32'h00000000
`define ETH_MIIADDRESS_DEF 32'h00000000
`define ETH_MIITX_DATA_DEF 32'h00000000
`define ETH_MIIRX_DATA_DEF 32'h00000000
`define ETH_MIISTATUS_DEF 32'h00000000
`define ETH_MAC_ADDR0_DEF 32'h00000000
`define ETH_MAC_ADDR1_DEF 32'h00000000
`define ETH_TX_BD_NUM_DEF 8'h80
