altera FPGA/CPLD高级篇(VHDL源代码)

						----- ! -------- W A R N I N G -------- ! -----
						----- ! -------- FIR COMPILER GENERATED FILE --- ! -----
						---------------------DO NOT ATTEMPT TO MODIFY! -----
				
				width = 13;
				depth = 13;
				addrex_radix = hex;
				data_radix = hex;
				
				content
				  begin
					0	: 0;
					1	: 0;
					2	: 0;
					3	: 0;
					4	: 0;
					5	: 0;
					6	: 0;
					7	: 0;
					8	: 0;
					9	: 0;
					a	: 0;
					b	: 0;
					c	: 0;
				END;