8*8位的fifo数据缓冲器的vhdl源程序。经过quartus ii 6.0 验证成功。

				8*8位的fifo数据缓冲器的vhdl源程序
				编了个8*8位的fifo数据缓冲器的vhdl源程序，是经过quartusII4.2编译成功的程序。。希望能跟各位交流
				library ieee;
				use ieee.std_logic_1164.all;
				entity fifo is
				 generic( w: integer :=8;  k: integer :=8 );
				 port (clk,reset,wr,rd :in std_logic;
				        din :in std_logic_vector( k-1 downto 0);
				       dout :out std_logic_vector( k-1 downto 0);
				       full,empty :out std_logic);
				end fifo;
				
				architecture fifo_arch of fifo is
				  type memory is array (0 to w-1) of std_logic_vector( k-1 downto 0);
				  signal ram:memory;
				  signal wp,rp: integer range 0 to w-1;
				  signal in_full,in_empty:std_logic;
				begin
				process(clk)
				  begin
				  if rising_edge(clk) then
				     if (wr='0' and in_full='0') then
				         ram(wp)				     end if;
				  end if;
				end process;
				
				process(clk,reset)
				  begin
				  if (reset='1') then
				     wp				  elsif rising_edge(clk) then
				     if (wr='0' and in_full='0') then
				         if(wp=w-1) then
				            wp				           else wp				          end if;
				     end if;
				   end if;
				end process;
				
				process(clk,reset)
				  begin
				  if (reset='1') then
				     rp				  elsif rising_edge(clk) then
				     if (rd='0' and in_empty='0') then
				         if(rp=w-1) then
				            rp				           else rp				          end if;
				     end if;
				   end if;
				end process;
				
				process(clk,reset)
				  begin
				  if (reset='1') then
				     in_empty				    elsif rising_edge(clk) then
				     if ((rp=wp-2 or (rp=w-1 and wp=1) or (rp=w-2 and wp=0)) and (rd='0' and wr='1'))then
				           in_empty				       elsif (in_empty='1' and wr='0') then
				           in_empty				     end if;
				   end if;
				end process;
				
				process(clk,reset)
				  begin
				   if (reset='1') then
				      in_full				    elsif  rising_edge(clk) then
				      if (rp=wp and wr='0' and rd='1') then
				         in_full				       elsif (in_full='1' and rd='0') then
				         in_full				       end if;
				    end if;
				end process;
				
				full				empty				dout				
				end fifo_arch;