在maxplusII上用VHDL语言编程实现的数字基带信号的同步提取

				library IEEE;
				use IEEE.std_logic_1164.all;
				
				entity store is
					port (
						   reset : in std_logic;
				            clr : in std_logic;
						   en : in std_logic;
						   keyvalue : in std_logic_vector (3 downto 0);
						   keyout : out std_logic_vector (31 downto 0)
					);
				end entity;
				
				
				architecture store_arch of store is
				signal a: std_logic_vector (31 downto 0);
				begin
				 keyout					process (reset,en)
					begin
				
						if reset='0' or clr='1' then
				        a				elsif (en'event and en='1')then
				if(keyvalue>=  "0000" and keyvalue				      a(31 downto 4)				      a(3 downto 0)				else    
				   	if(keyvalue="1100")then
				     a(27 downto 0)				    a(31 downto 28)				end if;
				end if;
				end if;	
				end process;
				end store_arch;