/****************************************************************************** * * File Name: txmit.v * Version: 1.1 * Date: January 22, 2000 * Model: Uart Chip * * Company: Xilinx * * * Disclaimer: THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY * WHATSOEVER AND XILINX SPECIFICALLY DISCLAIMS ANY * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR * A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT. * * Copyright (c) 2000 Xilinx, Inc. * All rights reserved * ******************************************************************************/ /****************************************************************************** Signal Direction Function rst Input Resets wrn1,wrn2,no_bits_sent, clkdiv[3:0],tbr[7:0],tsr[7:0] clk16x Input Local reference clock 16X the data rate wrn Input Control signal which strobes data from din[7:0] to tbr[7:0] sdo Output Serial data output tbre Output Status signal indication that the transmitter buffer register is empty no_bits_sent Internal Controls word_size and sequences transmitter operation clk1x_enable Internal Enables internal clock clk1x. tbr[7:0] Internal Accepts data from din[7:0] and transfers data to tsr[7:0] tsr[7:0] Internal Receives data from tbr[7:0] and shifts to sdo clkdiv[3:0] Internal Used in generation of internal clock ******************************************************************************/ `timescale 1 ns / 1 ns module txmit (din,tbre,tsre,rst,clk16x,wrn,sdo) ; output tbre ; output tsre ; output sdo ; input [7:0] din ; input rst ; input clk16x ; input wrn ; reg tbre ; reg tsre ; reg clk1x_enable ; reg [7:0] tsr ; reg [7:0] tbr ; reg parity ; reg[3:0] clkdiv ; wire clk1x ; reg sdo ; reg [3:0] no_bits_sent ; reg wrn1 ; reg wrn2 ; always @(posedge clk16x or posedge rst) begin if (rst) begin wrn1 wrn2 end else begin wrn1 wrn2 end end always @(posedge clk16x or posedge rst) begin if (rst) begin tbre clk1x_enable end else if (!wrn1 && wrn2) begin clk1x_enable tbre end else if (no_bits_sent == 4'b0010) tbre else if (no_bits_sent == 4'b1101) begin clk1x_enable tbre end end always @(negedge wrn or posedge rst) begin if (rst) tbr = 8'b0 ; else tbr = din ; end always @(posedge clk16x or posedge rst) begin if (rst) clkdiv = 4'b0 ; else if (clk1x_enable) clkdiv = clkdiv + 1 ; end assign clk1x = clkdiv[3] ; always @(negedge clk1x or posedge rst) if (rst) begin sdo tsre parity tsr end else begin if (no_bits_sent == 4'b0001) begin tsr tsre end else if (no_bits_sent == 4'b0010) begin sdo end else if ((no_bits_sent >= 4'b0011) && (no_bits_sent begin tsr[7:1] tsr[0] sdo parity end else if (no_bits_sent == 4'b1011) begin sdo end else if (no_bits_sent == 4'b1100) begin sdo tsre end end always @(posedge clk1x or posedge rst or negedge clk1x_enable) if (rst) no_bits_sent = 4'b0000 ; else if (!clk1x_enable) no_bits_sent = 4'b0000 ; else no_bits_sent = no_bits_sent + 1 ; endmodule
