Design and Test_Verilog HDL——EDA先锋工作室《设计与验证—Verilog HDL》配书源代码

源代码在线查看: state1.srm

软件大小: 1844 K
上传用户: ranzige
关键词: Test_Verilog HDL Verilog Design
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相关代码

				f "noname"; #file 0
				f "noname"; #file 1
				f "c:\eda\synplicity\fpga_81\lib\lucent\ec.v"; #file 2
				f "c:\prj\fsm_abc\state1\state1.v"; #file 3
				VNAME 'LUCENT.OB.PRIM'; # view id 0
				VNAME 'LUCENT.IB.PRIM'; # view id 1
				VNAME 'LUCENT.FD1S3AX.PRIM'; # view id 2
				VNAME 'work.state1.verilog'; # view id 3
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