verilog HDL 基础实验源码

				Flow Status : Successful - Wed Oct 12 10:23:02 2005
				Quartus II Version : 5.0 Build 148 04/26/2005 SJ Full Version
				Revision Name : add
				Top-level Entity Name : add
				Family : MAX7000S
				Device : EPM7128SLC84-15
				Timing Models : Final
				Met timing requirements : N/A
				Total macrocells : 21
				Total pins : 15