CPLD VHDL CODE非常好的参考资料

				Flow Status : Successful - Sat Apr 15 09:11:11 2006
				Quartus II Version : 5.0 Build 148 04/26/2005 SJ Full Version
				Revision Name : add
				Top-level Entity Name : add
				Family : MAX7000S
				Device : EPM7128SLC84-15
				Timing Models : Final
				Met timing requirements : N/A
				Total macrocells : 27
				Total pins : 22