FPGA编写的三角波发生器

				module sinwave(clkout,clkin);
				input clkin;
				output clkout;
				reg clkout;
				reg[10:0] temp=0;
				always@(posedge clkin)
				begin
					temp=temp+11'd1;
					if(temp==10)
					begin
						clkout=~clkout;
						temp=11'd0;
					end
				end
				endmodule