`include "register.v" `include "accum.v" `include "alu.v" `include "datact1.v" `include "adr.v" `include "counter.v" `include "machinect1.v" `include "machine.v" `include "addr_decode.v" `include "ram.v" `include "rom.v" `include "clk_gen.v" module riscmcu(clk,reset); input clk,reset; wire clk1; wire clk2; wire clk4; wire fetch; wire alu_clk; wire[7:0] data; wire ena; wire rst; wire alu_out; wire[7:0] accumout; wire zero; wire[2:0] opcode; wire[12:0] ir_addr,pc_addr; wire[12:0] addr; wire inc_pc; wire load_acc; wire load_pc; wire rd; wire wr; wire load_ir; wire datact1_ena; wire ram_sel; wire rom_sel; clk_gen clk_gen(clk,reset,clk1,clk2,clk4,fetch,alu_clk); register register({opcode,ir_addr},data,load_ir,clk1,reset); accum accum(accumout,alu_out,load_acc,clk1,reset); alu alu(alu_out,zero,data,accumout,alu_clk,opcode); datact1 datact1(data,alu_out,datact1_ena); adr adr(addr,fetch,ir_addr,pc_addr); counter counter(pc_addr,ir_addr,load_pc,inc_pc,reset); machinect1 machinect1(ena,fetch,reset); machine machine(inc_pc,load_acc,load_pc,rd,wr,load_ir,datact1_ena,halt,clk1,zero,ena,opcode); addr_decode addr_decode(addr,rom_sel,ram_sel); ram ram(data,addr[9:0],ram_sel,rd,wr); rom rom(data,addr,rd,rom_sel); endmodule
