FPGA-CPLD_DesignTool(8-9-10)源代码请需要的朋友下载
源代码在线查看： top.srd
f "noname"; #file 0
f "j:\example-8-1\modular_design\syn_top\virtex2.v"; #file 1
f "j:\example-8-1\modular_design\syn_top\top.v"; #file 2
VNAME 'work.module_c.verilog'; # view id 0
VNAME 'work.module_b.verilog'; # view id 1
VNAME 'work.module_a.verilog'; # view id 2
VNAME 'work.top.verilog'; # view id 3
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