//////////2006.05.11 capture dsss
module chip1(clk,out,reset,t1);//ok
input clk,reset,t1;
output out;
reg c1,c2,c3,c4,flag;
reg out;
reg[4:0]n;
reg red;
//reg[7:0]flag;
/*initial
begin
c1 c2 c3 c4 flag end
*/
always @(posedge clk)// up edg
begin
if(reset==1)//1+x+x^4//0xf590=1111 0101 1001 000B init
begin
c1 c2 c3 c4 flag // light(red);
end
if(n>10) // move 1 bit to left
begin
// for(n=2;n out c4 c3 c2 c1 n end
else //n begin
if(t1==1) // detect and change phase
begin
if(flag==0) //first change phase
begin
n // n flag end
else
begin
n end
end
else
begin
n end
end
if(t1==0) //ti=0 flag=0,prevent repeat change phase
begin
flag end
end
/*always @(posedge t1)// up edg
begin
flag
end
*/
/*task light(color);
output color;
begin
color end
endtask
*/
endmodule
/*module chip2(t1,out);//ok
input t1;
output out;
//reg[7:0]n;
reg out;
always @(posedge t1)// up edg
begin
// defparam
// n=n+1;
out=~out;
end
endmodule
*/
/*module chip1(clk, in, reset, out);
input clk, in, reset;
output out;
reg out;
reg state;
parameter s0 = 0, s1 = 1;
always @(state)
begin
case (state)
s0:
out = 0;
s1:
out = 1;
default:
out = 0;
endcase
end
endmodule
*/
