应用VHDL设计的8b10b 编码器
源代码在线查看： func_sim.do
# 8b/10b Functional Simulation ModelSim DO file
# Create work library
vlib work
# Compile package files
vcom -just e -93 -explicit -work work pkg_convert.vhd
vcom -skip e -93 -explicit -work work pkg_convert.vhd
vcom -just e -93 -explicit -work work pkg_spc_char.vhd
vcom -skip e -93 -explicit -work work pkg_spc_char.vhd
# Compile encoder files
vcom -just e -93 -explicit enc_func.vhd
vcom -skip e -93 -explicit enc_func.vhd
vcom -just e -93 -explicit s_gen.vhd
vcom -skip e -93 -explicit s_gen.vhd
vcom -just e -93 -explicit dis_gen.vhd
vcom -skip e -93 -explicit dis_gen.vhd
vcom -just e -93 -explicit main_enc.vhd
vcom -skip e -93 -explicit main_enc.vhd
# Compile decoder files
vcom -just e -93 -explicit err_check.vhd
vcom -skip e -93 -explicit err_check.vhd
vcom -just e -93 -explicit dec_func.vhd
vcom -skip e -93 -explicit dec_func.vhd
vcom -just e -93 -explicit main_dec.vhd
vcom -skip e -93 -explicit main_dec.vhd
# Compile test bench files
vcom -just e -93 -explicit tst_bench.vhd
vcom -skip e -93 -explicit tst_bench.vhd
vcom -just e -93 -explicit main_tb.vhd
vcom -skip e -93 -explicit main_tb.vhd
# Load simulation: main_tb
vsim -t 1ps -L unisims -lib work main_tb
# View wave window and run wave.do
view wave
do wave.do
view structure
view signals
# Simulation time
run 45us
