FPGA-CPLD_DesignTool(8-9-10)源代码

				set -tmpdir __projnav
				set -xsthdpdir ./xst
				run
				-ifn stopwatch.prj
				-ifmt VHDL
				-ofn stopwatch
				-ofmt NGC
				-p xc2v40-5fg256
				-ent stopwatch
				-opt_mode Speed
				-opt_level 1
				-iuc NO
				-keep_hierarchy NO
				-glob_opt AllClockNets
				-rtlview Yes
				-read_cores YES
				-write_timing_constraints NO
				-cross_clock_analysis NO
				-hierarchy_separator _
				-bus_delimiter 
				-case lower
				-slice_utilization_ratio 100
				-fsm_extract YES -fsm_encoding Auto
				-ram_extract Yes
				-ram_style Auto
				-rom_extract Yes
				-mux_extract YES
				-mux_style Auto
				-decoder_extract YES
				-priority_extract YES
				-shreg_extract YES
				-shift_extract YES
				-xor_collapse YES
				-resource_sharing YES
				-complex_clken YES
				-mult_style auto
				-iobuf YES
				-max_fanout 500
				-bufg 16
				-register_duplication YES
				-equivalent_register_removal YES
				-register_balancing No
				-slice_packing YES
				-iob auto
				-slice_utilization_ratio_maxmargin 5