FPGA-CPLD_DesignTool(8-9-10)源代码

				@P:  Worst Slack : 0.884
				@P:  clk - Estimated Frequency : 131.7 MHz
				@P:  clk - Requested Frequency : 100.0 MHz
				@P:  clk - Estimated Period : 7.594
				@P:  clk - Requested Period : 10.000
				@P:  clk - Slack : 2.406
				@P:  stopwatch|XLXI_16.CLK0_BUF_derived_clock - Estimated Frequency : 138.7 MHz
				@P:  stopwatch|XLXI_16.CLK0_BUF_derived_clock - Requested Frequency : 100.0 MHz
				@P:  stopwatch|XLXI_16.CLK0_BUF_derived_clock - Estimated Period : 7.210
				@P:  stopwatch|XLXI_16.CLK0_BUF_derived_clock - Requested Period : 10.000
				@P:  stopwatch|XLXI_16.CLK0_BUF_derived_clock - Slack : 2.790
				@P:  stopwatch|rst_int_inferred_clock - Estimated Frequency : 109.7 MHz
				@P:  stopwatch|rst_int_inferred_clock - Requested Frequency : 100.0 MHz
				@P:  stopwatch|rst_int_inferred_clock - Estimated Period : 9.116
				@P:  stopwatch|rst_int_inferred_clock - Requested Period : 10.000
				@P:  stopwatch|rst_int_inferred_clock - Slack : 0.884
				@P:  System - Estimated Frequency : 149.0 MHz
				@P:  System - Requested Frequency : 100.0 MHz
				@P:  System - Estimated Period : 6.713
				@P:  System - Requested Period : 10.000
				@P:  System - Slack : 3.287
				@P: stopwatch Part : xc2v80fg256-6
				@P: stopwatch I/O primitives : 27
				@P: stopwatch I/O Register bits : 0
				@P: stopwatch Register bits (Non I/O) : 15 (1%)
				@P: stopwatch Total Luts : 47 (4%)