FPGA-CPLD_DesignTool(example5-6）
源代码在线查看： prescale_counter.pcf
SCHEMATIC START ;
// created by map version F.25 on Sat Dec 28 11:52:12 2002
COMP "reset" LOCATE = SITE "L26" LEVEL 1;
TIMEGRP "clk" = BEL "counter_2" BEL "counter_3" BEL "counter_4" BEL "counter_5"
BEL "counter_6" BEL "counter_7" BEL "counter_8" BEL "counter_9" BEL "counter_10"
BEL "counter_11" BEL "counter_12" BEL "counter_13" BEL "counter_14" BEL
"counter_15" BEL "counter_16" BEL "counter_17" BEL "counter_18" BEL "counter_19"
BEL "counter_20" BEL "counter_21" BEL "counter_22" BEL "counter_23" BEL
"counter_24" BEL "counter_25" BEL "counter_26" BEL "counter_27" BEL "counter_28"
BEL "counter_29" BEL "counter_30" BEL "counter_31" BEL "counter_0" BEL
"counter_1" ;
TIMEGRP "lower_counter" = BEL "counter_0" BEL "counter_1" ;
TIMEGRP "upper_counter" = FFS ("*") EXCEPT TIMEGRP "lower_counter" ;
TS_clk = PERIOD TIMEGRP "clk" 5 nS HIGH 50.000000 % ;
TS_upper_counter = MAXDELAY FROM TIMEGRP "upper_counter" TO TIMEGRP
"upper_counter" TS_clk * 4.000 ;
OFFSET = OUT 10 nS AFTER COMP "clk" ;
SCHEMATIC END ;
