此文件是对xilinx95144器件编的程序
源代码在线查看： reg2_4.data
MODELDATA
MODELDATA_VERSION "v1998.8"
DESIGN "reg2_4";
/* port drive, load, max capacitance and max transition in data file */
PORTDATA
reset: MAXTRANS(0.0);
wr: MAXTRANS(0.0);
cs: MAXTRANS(0.0);
din: MAXTRANS(0.0);
din: MAXTRANS(0.0);
din: MAXTRANS(0.0);
dout: MAXTRANS(0.0);
dout: MAXTRANS(0.0);
dout: MAXTRANS(0.0);
dout: MAXTRANS(0.0);
ENDPORTDATA
/* timing arc data */
TIMINGDATA
ARCDATA
wr_dout_delay:
CELL_RISE(scalar) {
VALUES("4.5");
}
CELL_FALL(scalar) {
VALUES("4.5");
}
ENDARCDATA
ARCDATA
wr_dout_delay:
CELL_RISE(scalar) {
VALUES("4.5");
}
CELL_FALL(scalar) {
VALUES("4.5");
}
ENDARCDATA
ARCDATA
wr_dout_delay:
CELL_RISE(scalar) {
VALUES("4.5");
}
CELL_FALL(scalar) {
VALUES("4.5");
}
ENDARCDATA
ARCDATA
wr_dout_delay:
CELL_RISE(scalar) {
VALUES("4.5");
}
CELL_FALL(scalar) {
VALUES("4.5");
}
ENDARCDATA
ARCDATA
cs_wr_setup:
CONSTRAINT(scalar) {
VALUES("6");
}
ENDARCDATA
ARCDATA
din_wr_setup:
CONSTRAINT(scalar) {
VALUES("6");
}
ENDARCDATA
ARCDATA
din_wr_setup:
CONSTRAINT(scalar) {
VALUES("6");
}
ENDARCDATA
ARCDATA
din_wr_setup:
CONSTRAINT(scalar) {
VALUES("6");
}
ENDARCDATA
ARCDATA
cs_wr_hold:
CONSTRAINT(scalar) {
VALUES("-1.5");
}
ENDARCDATA
ARCDATA
din_wr_hold:
CONSTRAINT(scalar) {
VALUES("-1.5");
}
ENDARCDATA
ARCDATA
din_wr_hold:
CONSTRAINT(scalar) {
VALUES("-1.5");
}
ENDARCDATA
ARCDATA
din_wr_hold:
CONSTRAINT(scalar) {
VALUES("-1.5");
}
ENDARCDATA
ENDTIMINGDATA
ENDMODELDATA
