FPGA驱动STN （16x2）的程序
源代码在线查看： clk_div.v
`timescale 1ns / 100ps
module clk_div(
//input port
clk_in, // 50Mhz
rst_n,
//output port
clk_out // 1s
);
//input signal
input clk_in;
input rst_n;
//output signal
output clk_out;
//internal
reg clk_out;
reg [9:0] count1;
reg [9:0] count2;
reg [5:0] count3;
reg clk_dly1;
reg clk_dly2;
//
parameter DLY = 1;
//-----------------------main code----------------------------
always @(posedge clk_in or negedge rst_n)
begin
if(!rst_n)
count1 else if(count1 == 10'b11111_01000) // 1000
count1 else
count1 end
always @(posedge clk_in or negedge rst_n)
begin
if(!rst_n)
clk_dly1 else if(count1 == 10'b11111_01000) // 1000
clk_dly1 else
clk_dly1 end
always @(posedge clk_dly1 or negedge rst_n)
begin
if(!rst_n)
count2 else if(count2 == 10'b11111_01000) // 1000
count2 else
count2 end
always @(posedge clk_dly1 or negedge rst_n)
begin
if(!rst_n)
clk_dly2 else if(count2 == 10'b11111_01000) // 1000
clk_dly2 else
clk_dly2 end
always @(posedge clk_dly2 or negedge rst_n)
begin
if(!rst_n)
count3 else if(count3 == 6'b00_011) // 3
count3 else
count3 end
always @(posedge clk_dly2 or negedge rst_n)
begin
if(!rst_n)
clk_out else if(count3 == 6'b00_011) // 3
clk_out else
clk_out end
endmodule
