library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity clock is port
( inclk: in std_logic;
keyclr:in std_logic;
oe1 :out std_logic;
oe2 :out std_logic;
dir1 :out std_logic;
dir2 :out std_logic;
outseg:out std_logic_vector(7 downto 0);
outbit:out std_logic_vector(7 downto 0));
end clock;
Architecture a_counter of clock is
signal ma,mb,mc,md,me,mf,mg,mh,mseg:std_logic_vector(3 downto 0);
signal lm ,hm: std_logic_vector(16 downto 0);
signal fpa,fpb: std_logic;
signal st: std_logic_vector(2 downto 0);
begin
process(inclk)
begin
if (inclk'event and inclk='1') then
if lm=24999 then
lm else
lm end if;
end if;
end process;
process(fpa)
begin
if (fpa'event and fpa='1') then
if hm=499 then
hm else
hm end if;
end if;
end process;
process(fpb)
begin
if (keyclr='0') then
ma md else if (fpb'event and fpb='1') then
mg mh if ma=9 then
ma if mb=5 then
mb if mc=9 then
mc if md=5 then
md if(me=3 and mf=2)then
me else
if me=9 then
mf else
me end if;
end if;
else
md end if;
else
mc end if;
else
mb end if;
else
ma end if;
end if;
end if;
end process;
process (fpa)
begin
if(fpa'event and fpa='1') then
st end if;
end process;
process (st)
begin
case st is
when "000" =>
mseg outbit when "001"=>
mseg outbit when "010"=>
mseg outbit when "011"=>
mseg outbit when "100"=>
mseg outbit when "101"=>
mseg outbit when "110"=>
mseg outbit when "111"=>
mseg outbit when others=>outbit end case;
end process;
Process(mc)
begin
case mseg is
when "0001"=> outseg when "0010"=> outseg when "0011"=> outseg when "0100"=> outseg when "0101"=> outseg when "0110"=> outseg when "0111"=> outseg when "1000"=> outseg when "1001"=> outseg when "1010"=> outseg when "1011"=> outseg when "1100"=> outseg when "1101"=> outseg when "1110"=> outseg when "1111"=> outseg when others=> outseg end case;
end process;
oe1 dir1 oe2 dir2
end a_counter;
