FPGA开发板上写的Verilog代码 功能是从电脑端发送一个字节

				//-----------------------------------------------------------------
				// This is the top level module that ties all sub-modules together
				// Filename : counter.v
				//-----------------------------------------------------------------
				
				module counter(clk,reset,one_out,ten_out);
				    input clk;
				    input reset;
				    output [3:0] one_out;
				    output [3:0] ten_out;
				
				    wire nreset;
				    wire ones_en;        //Chip enable in digital one
				    wire tens_en;        //Chip enable in digital ten
				    wire tc_ones;        //Carry out in digital one
				    wire [3:0] one_out;	//BCD output in digital one
				    wire [3:0] ten_out;	//DCD output in digital ten
				
					              
				cnt_10 ONES(
				            .ce(ones_en),
				            .clk(clk),
				            .clr(nreset),
				            .tc(tc_ones),
				            .qout(one_out)
				           );
						   
				cnt_10 TENS(
				            .ce(tens_en),
				            .clk(clk),
				            .clr(nreset),
				            .tc(),
				            .qout(ten_out)
				           );
						   
				assign tens_en = tc_ones;
				assign ones_en = 1'b1;
				
				assign nreset  = ~reset;
				
				endmodule