这是著名的硬件调试工具debussy的教学说明
源代码在线查看: lastsession.ses
@Debussy rc file Version 1.0 [FSM.1] viewport = 732 94 387 479 DesignName = "DebussyLib" ModuleName = "BJkernel#__fsm__0" InstName = "system.i_BJkernel.BJkernel:FSM0:61:160:FSM" ViewRatio = 0.231 CenterXY = 74 807 ShowDefaultView = FALSE ShowStateAction = FALSE ShowTransAction = FALSE ShowTransCond = FALSE ShowLinkAlways = FALSE ShowToolbar = TRUE ShowMsgLine = TRUE StateAnimation = TRUE [KeyNote] Line1 = The last exit status session file [PartialView.1] Title = "" Gate0 = "system.i_BJkernel.BJkernel:FSM0:61:160:FSM" 1500 2500 globalInfo = "DebussyLib" 0 0 1 0 0 bHierFSM = True [PartialView.2] Title = "View Trace Unknown Result" Port0 = 2 "system.OK" 1 Gate0 = "system.i_BJkernel.BJkernel:FSM0:61:160:FSM" 1500 2500 "Card[3:0]" "BJ_clock" "NewGame" "NewCard" "reset" "NextCard" "Fail" "Total[4:0]" "Ace" ConnUp0 = 1 "system.i_BJkernel.OK" 1 "system.OK" 8000 5875 globalInfo = "DebussyLib" 1 0 1 0 1 [hb] viewport = 35 54 711 545 141 317 178 0 activeNode = "system" interactiveMode = False viewType = Source simulatorMode = False postSimFile = /ae9b/hlhsiao/testcase/demo43/verilog/rtl/verilog.fsdb sourceBeginLine = 22 baMode = False cmdToolbar = True simToolbar = True baToolbar = True srcLineNum = True syncSignal = False syncTime = 0 traceMode = Hierarchical showTraceInSchema = True Scope1 = "system" [imp.design1] dbEnum = oh invokeDir = /ae9b/hlhsiao/testcase/demo43/verilog/rtl design = DebussyLib hostCommand = -f run.f [memoryWindow] count = 0 [schematics.0] viewport = 434 340 638 516 viewbbox = -1190 -506 11690 7880 design = . "system.i_BJkernel" DebussyLib schmaticId = 2 partial = False partialHier = False display_port_name = False display_pin_name = False display_instance_name = False display_local_net_name = False display_back_annotation = False display_back_annotation_in_Line = False display_param_list = False auto_fit_select_set = False pre_select = True show_full_name = False display_short_name = True append_view_obj = True cmdToolbar = True msgToolbar = True syncTime = 0 traceMode = Hierarchical Scope0 = . "system" -4912 -2600 22118 15000 Scope1 = . "system.i_BJsource" -4163 -631 17163 13255 [schematics.1] viewport = 469 335 638 516 viewbbox = -1506 1500 7708 7500 design = . "" DebussyLib schmaticId = 4 partial = True partialHier = False partialSessionFile = PartialView.1 display_port_name = False display_pin_name = False display_instance_name = False display_local_net_name = False display_back_annotation = False display_back_annotation_in_Line = False display_param_list = False auto_fit_select_set = False pre_select = True show_full_name = False display_short_name = True append_view_obj = True cmdToolbar = True msgToolbar = True syncTime = 0 traceMode = Hierarchical [schematics.2] viewport = 504 330 638 516 viewbbox = 432 974 11482 8168 design = . "" DebussyLib schmaticId = 7 partial = True partialHier = False partialSessionFile = PartialView.2 display_port_name = False display_pin_name = False display_instance_name = False display_local_net_name = False display_back_annotation = True display_back_annotation_in_Line = False display_param_list = False auto_fit_select_set = False pre_select = True show_full_name = False display_short_name = True append_view_obj = True cmdToolbar = True msgToolbar = True syncTime = 0 traceMode = Hierarchical [wave.0] viewPort = 36 481 670 386 83 56 SessionFile = /ae9b/hlhsiao/testcase/demo43/verilog/rtl/DebussyLog/lastSession.ses.wave.0 displayGrid = FALSE hierarchicalName = FALSE snap = TRUE displayLeadingZeros = FALSE fixDelta = FALSE displayCursorMarker = FALSE autoUpdate = FALSE displayGlitchs = FALSE ignoreGlitchs = FALSE highlightGlitchs = FALSE waveformSync = FALSE displayErrors = TRUE displayMsgSymbols = TRUE showMsgDescriptions = TRUE autoFit = FALSE displayDeltaY = FALSE centerCursor = FALSE