DE1-FPGA-Board
源代码在线查看： clock.v
//
// FPGA PACMAN clock generator
//
module clock(
I_CLK_18M,
O_CLK_12M,
O_CLK_06M,
O_CLK_06Mn
);
input I_CLK_18M;
output O_CLK_12M;
output O_CLK_06M;
output O_CLK_06Mn;
// 2/3 clock divider(duty 33%)
reg [1:0] clk_ff1,clk_ff2;
//I_CLK 1010101010101010101
//c_ff10 0011110011110011110
//c_ff11 0011000011000011000
//c_ff20 0000110000110000110
//c_ff21 0110000110000110000
//O_12M 0000110110110110110
always @(posedge I_CLK_18M)
begin
clk_ff1[0] clk_ff1[1] clk_ff2[0] end
always @(negedge I_CLK_18M)
clk_ff2[1]
// 2/3 clock (duty 66%)
assign O_CLK_12M = clk_ff2[0]| clk_ff2[1];
// 1/3 clock divider (duty 50%)
reg CLK_6M , CLK_6Mn;
always @(posedge O_CLK_12M)
begin
CLK_6Mn CLK_6M end
assign O_CLK_06M = CLK_6M;
assign O_CLK_06Mn = CLK_6Mn;
endmodule
