# begin LFP file D:\FPGA\TEST\xc_9572\top.lfp
designfile top.ngd
IO_GROUP "MR_2" ;
IO_GROUP "MR_1" ;
IO_GROUP "MR_0" ;
IO_GROUP "D" ;
IO_GROUP "D" ;
NET "WR" COLOR=6 ;
NET "UART0" COLOR=6 ;
NET "SPD2A" COLOR=6 ;
NET "SPDB2" COLOR=6 ;
NET "SPDB1" COLOR=6 ;
NET "SPDA1" COLOR=6 ;
NET "SEN2" COLOR=6 ;
NET "SEN1" COLOR=6 ;
NET "SEN0" COLOR=6 ;
NET "RESET" COLOR=6 ;
NET "REL0" COLOR=6 ;
NET "PC2ON" COLOR=6 ;
NET "PC1ON" COLOR=6 ;
NET "M2SG" COLOR=6 ;
NET "M2PS" COLOR=6 ;
NET "M2CLR" COLOR=6 ;
NET "M1SG" COLOR=6 ;
NET "M1PS" COLOR=6 ;
NET "M1CLR" COLOR=6 ;
NET "MR_2" COLOR=6 IO_GROUP="MR_2" ;
NET "MR_2" COLOR=6 IO_GROUP="MR_2" ;
NET "MR_2" COLOR=6 IO_GROUP="MR_2" ;
NET "MR_2" COLOR=6 IO_GROUP="MR_2" ;
NET "MR_2" COLOR=6 IO_GROUP="MR_2" ;
NET "MR_2" COLOR=6 IO_GROUP="MR_2" ;
NET "MR_2" COLOR=6 IO_GROUP="MR_2" ;
NET "MR_2" COLOR=6 IO_GROUP="MR_2" ;
NET "MR_1" COLOR=6 IO_GROUP="MR_1" ;
NET "MR_1" COLOR=6 IO_GROUP="MR_1" ;
NET "MR_1" COLOR=6 IO_GROUP="MR_1" ;
NET "MR_1" COLOR=6 IO_GROUP="MR_1" ;
NET "MR_1" COLOR=6 IO_GROUP="MR_1" ;
NET "MR_1" COLOR=6 IO_GROUP="MR_1" ;
NET "MR_1" COLOR=6 IO_GROUP="MR_1" ;
NET "MR_1" COLOR=6 IO_GROUP="MR_1" ;
NET "MR_0" COLOR=6 IO_GROUP="MR_0" ;
NET "MR_0" COLOR=6 IO_GROUP="MR_0" ;
NET "MR_0" COLOR=6 IO_GROUP="MR_0" ;
NET "MR_0" COLOR=6 IO_GROUP="MR_0" ;
NET "MR_0" COLOR=6 IO_GROUP="MR_0" ;
NET "MR_0" COLOR=6 IO_GROUP="MR_0" ;
NET "MR_0" COLOR=6 IO_GROUP="MR_0" ;
NET "MR_0" COLOR=6 IO_GROUP="MR_0" ;
NET "INT0" COLOR=6 ;
NET "INT_L0" COLOR=6 ;
NET "D" COLOR=6 IO_GROUP="D" ;
NET "D" COLOR=6 IO_GROUP="D" ;
NET "D" COLOR=6 IO_GROUP="D" ;
NET "D" COLOR=6 IO_GROUP="D" ;
NET "D" COLOR=6 IO_GROUP="D" ;
NET "D" COLOR=6 IO_GROUP="D" ;
NET "D" COLOR=6 IO_GROUP="D" ;
NET "D" COLOR=6 IO_GROUP="D" ;
NET "CS1" COLOR=6 ;
NET "CS" COLOR=6 ;
NET "CLK8" COLOR=6 ;
NET "CLK" COLOR=6 ;
NET "A2" COLOR=6 ;
NET "A1" COLOR=6 ;
NET "A0" COLOR=6 ;
NET "ALMR" COLOR=6 ;
INST "XLXI_36" COLOR=8 ;
INST "XLXI_36/XLXI_1" COLOR=9 ;
INST "XLXI_36/XLXI_3" COLOR=10 ;
