verilog数字系统设计教程 所有例题的源程

				//?????
				//------------------------------------------------------------------------------
				module counter ( pc_addr, ir_addr, load, clock, rst);
				output [12:0] pc_addr;
				input [12:0] ir_addr;
				input load, clock, rst;
				reg [12:0] pc_addr;
				
				always @( posedge clock or posedge rst )
				begin
				if(rst)
				pc_addr				else
				if(load)
				pc_addr				else
				pc_addr 				end
				endmodule
				//------------------------------------------------------------------------------