synplify环境下 实现 全加器 功能

				#-- Synplicity, Inc.
				#-- Version 7.3.1     
				#-- Project file D:\YHQProj\Synplify\Full_adder.prj
				#-- Written on Mon Feb 02 09:38:11 2004
				
				
				#add_file options
				
				
				#implementation: "rev_1"
				impl -add rev_1
				
				#device options
				set_option -technology SPARTAN2E
				set_option -part XC2S50E
				set_option -package FT256
				set_option -speed_grade -7
				
				#compilation/mapping options
				set_option -default_enum_encoding default
				set_option -symbolic_fsm_compiler 1
				set_option -resource_sharing 1
				set_option -use_fsm_explorer 0
				
				#map options
				set_option -frequency 1.000
				set_option -fanout_limit 100
				set_option -disable_io_insertion 0
				set_option -pipe 0
				set_option -update_models_cp 0
				set_option -verification_mode 0
				set_option -fixgatedclocks 0
				set_option -modular 0
				set_option -retiming 0
				
				#simulation options
				set_option -write_verilog 0
				set_option -write_vhdl 0
				
				#automatic place and route (vendor) options
				set_option -write_apr_constraint 1
				
				#set result format/file last
				project -result_file "rev_1/Full_adder.edf"
				
				#implementation attributes
				set_option -vlog_std v2001
				set_option -auto_constrain_io 0
				impl -active "rev_1"