设计与验证verilog hdl
源代码在线查看: clk_3div.srm
f "noname"; #file 0
f "c:\prj\example-4-14\clk_3div\clk_3div.v"; #file 1
VNAME 'ispmach4s.MACH_DFF.prim'; # view id 0
VNAME 'ispmach4s.DFFRH.prim'; # view id 1
VNAME 'ispmach4s.IBUF.prim'; # view id 2
VNAME 'ispmach4s.OBUF.prim'; # view id 3
VNAME 'ispmach4s.INV.prim'; # view id 4
VNAME 'ispmach4s.AND2.prim'; # view id 5
VNAME 'work.clk_3div.verilog'; # view id 6
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