设计与验证verilog hdl

				f "noname"; #file 0
				f "c:\eda\synplicity\fpga_81\lib\xilinx\unisim.v"; #file 1
				f "c:\prj\example-4-7\clk_div_phase\clk_div_phase.v"; #file 2
				VNAME 'work.clk_div_phase.verilog'; # view id 0
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