verilog大量源程序

				/*	4-1 SELECTOR	*/
				module	SEL	( A, B, C, D, SEL, F );
				   input	A, B, C, D;
				   input	[1:0] SEL;
				   output	F ;
				   wire	SEL1_NOT, SEL0_NOT, AND1, AND2, AND3, AND4;
					
				   not	U1	( SEL1_NOT, SEL[1] ),
				       U2	( SEL0_NOT, SEL[0] );
				   and	U3	( AND1, A, SEL1_NOT, SEL0_NOT ),
						  U4	( AND2, B, SEL1_NOT, SEL[0] ),
						  U5	( AND3, C, SEL[1]  , SEL0_NOT ),
						  U6	( AND4, D, SEL[1]  , SEL[0] );
				   or	 U7	( F, AND1, AND2, AND3, AND4 );
				endmodule