//////////////////////////////////////////////////////////////////////
//// ////
//// 8051 indirect address ////
//// ////
//// This file is part of the 8051 cores project ////
//// http://www.opencores.org/cores/8051/ ////
//// ////
//// Description ////
//// Contains ragister 0 and register 1. used for indirrect ////
//// addressing. ////
//// ////
//// To Do: ////
//// nothing ////
//// ////
//// Author(s): ////
//// - Simon Teran, simont@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: oc8051_indi_addr.v,v $ // Revision 1.4 2002/09/30 17:33:59 simont // prepared header //
//
// synopsys translate_off
`include "oc8051_timescale.v"
// synopsys translate_on
module oc8051_indi_addr (clk, rst, addr, data_in, wr, wr_bit, data_out, sel, bank);
//
// clk (in) clock
// rst (in) reset
// addr (in) write address [oc8051_ram_wr_sel.out]
// data_in (in) data input (alu destination1) [oc8051_alu.des1]
// wr (in) write [oc8051_decoder.wr -r]
// wr_bit (in) write bit addresable [oc8051_decoder.bit_addr -r]
// data_out (out) data output [oc8051_ram_rd_sel.ri, oc8051_ram_wr_sel.ri -r]
// sel (in) select register [oc8051_op_select.op1_out[0] ]
// bank (in) select register bank: [oc8051_psw.data_out[4:3] ]
//
input clk, rst, wr, sel, wr_bit;
input [1:0] bank;
input [7:0] addr, data_in;
output [7:0] data_out;
reg [7:0] buff [7:0];
//
//write to buffer
always @(posedge clk or posedge rst)
begin
if (rst) begin
buff[3'b000] = #1 8'h00;
buff[3'b001] = #1 8'h00;
buff[3'b010] = #1 8'h00;
buff[3'b011] = #1 8'h00;
buff[3'b100] = #1 8'h00;
buff[3'b101] = #1 8'h00;
buff[3'b110] = #1 8'h00;
buff[3'b111] = #1 8'h00;
end else begin
if ((wr) & !(wr_bit)) begin
case (addr)
8'h00: buff[3'b000] = #1 data_in;
8'h01: buff[3'b001] = #1 data_in;
8'h08: buff[3'b010] = #1 data_in;
8'h09: buff[3'b011] = #1 data_in;
8'h10: buff[3'b100] = #1 data_in;
8'h11: buff[3'b101] = #1 data_in;
8'h18: buff[3'b110] = #1 data_in;
8'h19: buff[3'b111] = #1 data_in;
endcase
end
end
end
//
//read from buffer
assign data_out = (({3'b000, bank, 2'b00, sel}==addr) & (wr)) ?
data_in : buff[{bank, sel}];
endmodule
