VHDL实例,适合大家学习使用

				#$ TOOL ispDesignEXPERT 8.4
				#$ DATE Wed Feb 27 11:10:30 2002
				#$ TITLE cout.bls 
				#$ MODULE cout
				#$ PINS 25 M6 M5 M4 M3 M2 M1 M0 B6 B5 B4 B3 B2 B1 B0 MB7 MB6 MB5 MB4 MB3 MB2 MB1 MB0 EN CLR CLK
				#$ NODES 6 N_2 N_3 N_4 N_5 N_1 I1>CY
				#$ INTERFACE cdt10  8 CLK'i'  CLR'i'  EN'i'  CY'o'  Q0'o'  Q1'o'  Q2'o'  Q3'o' 
				#$ INTERFACE cdt6  7 CLK'i'  CLR'i'  EN'i'  CY'o'  Q0'o'  Q1'o'  Q2'o' 
				#$ INSTANCE I6 cdt10 8 CLR N_3 CLK N_2 M0 M1 M2 M3
				#$ INSTANCE I7 cdt10 8 CLR N_5 CLK N_4 B0 B1 B2 B3
				#$ INSTANCE I8 cdt10 8 CLR EN CLK N_1 MB0 MB1 MB2 MB3
				#$ INSTANCE I9 cdt10 8 CLR N_1 CLK N_5 MB4 MB5 MB6 MB7
				#$ INSTANCE I1 cdt6 7 CLK CLR N_2 I1>CY M4 M5 M6
				#$ INSTANCE I2 cdt6 7 CLK CLR N_4 N_3 B4 B5 B6
				
				.model cout
				.inputs
				.outputs
				.end