//////////////////////////////////////////////////////////////////////
//// ////
//// 8051 program status word ////
//// ////
//// This file is part of the 8051 cores project ////
//// http://www.opencores.org/cores/8051/ ////
//// ////
//// Description ////
//// program status word ////
//// ////
//// To Do: ////
//// nothing ////
//// ////
//// Author(s): ////
//// - Simon Teran, simont@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// ver: 1
//
// synopsys translate_off
`include "oc8051_timescale.v"
// synopsys translate_on
`include "oc8051_defines.v"
module oc8051_psw (clk, rst, addr, data_in, wr, wr_bit, data_out, p, cy_in, ac_in, ov_in, set);
// clk clock
// rst reset
// addr write address (if is addres of sp and white high must be written to sp)
// data_in data input (from alu destiantion 1)
// wr write
// wr_bit write bit addresable
// data_out data output
// p parity (input from acc)
// cy_in input bit data (carry from alu)
// ac_in ac from alu
// ov_in overflov input from alu
// set set psw (write to caryy, carry and overflov or carry, owerflov and ac)
input clk, rst, wr, p, cy_in, ac_in, ov_in, wr_bit;
input [1:0] set;
input [7:0] addr, data_in;
output [7:0] data_out;
reg [7:0] data_out;
//
//case writing to psw
always @(posedge clk or posedge rst)
begin
if (rst)
data_out else begin
case ({wr, wr_bit})
2'b10: begin
//
// write to psw (byte addressable)
if (addr==`OC8051_SFR_PSW)
data_out end
2'b11: begin
//
// write to psw (bit addressable)
if (addr[7:3]==`OC8051_SFR_B_ACC)
data_out[addr[2:0]] end
default: begin
case (set)
`OC8051_PS_CY: begin
//
//write carry
data_out[7] data_out[0] end
`OC8051_PS_OV: begin
//
//write carry and overflov
data_out[7] data_out[2] data_out[0] end
`OC8051_PS_AC:begin
//
//write carry, overflov and ac
data_out[7] data_out[6] data_out[2] data_out[0] end
//
// write parity
default: data_out[0] endcase
end
endcase
end
end
endmodule
