`include "eth_defines.v"
`include "timescale.v"
module eth_spram_256x32(
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, addr, di, do
`ifdef ETH_BIST
,
// debug chain signals
scanb_rst, // bist scan reset
scanb_clk, // bist scan clock
scanb_si, // bist scan serial in
scanb_so, // bist scan serial out
scanb_en // bist scan shift enable
`endif
);
//
// Generic synchronous single-port RAM interface
//
input clk; // Clock, rising edge
input rst; // Reset, active high
input ce; // Chip enable input, active high
input we; // Write enable input, active high
input oe; // Output enable input, active high
input [7:0] addr; // address bus inputs
input [31:0] di; // input data bus
output [31:0] do; // output data bus
`ifdef ETH_BIST
input scanb_rst; // bist scan reset
input scanb_clk; // bist scan clock
input scanb_si; // bist scan serial in
output scanb_so; // bist scan serial out
input scanb_en; // bist scan shift enable
`endif
`ifdef ETH_XILINX_RAMB4
RAMB4_S16 ram0
(
.DO (do[15:0]),
.ADDR (addr),
.DI (di[15:0]),
.EN (ce),
.CLK (clk),
.WE (we),
.RST (rst)
);
RAMB4_S16 ram1
(
.DO (do[31:16]),
.ADDR (addr),
.DI (di[31:16]),
.EN (ce),
.CLK (clk),
.WE (we),
.RST (rst)
);
`else // !ETH_XILINX_RAMB4
`ifdef ETH_VIRTUAL_SILICON_RAM
`ifdef ETH_BIST
vs_hdsp_256x32_bist ram0_bist
`else
vs_hdsp_256x32 ram0
`endif
(
.CK (clk),
.CEN (!ce),
.WEN (!we),
.OEN (!oe),
.ADR (addr),
.DI (di),
.DOUT (do)
`ifdef ETH_BIST
,
// debug chain signals
.scanb_rst (scanb_rst),
.scanb_clk (scanb_clk),
.scanb_si (scanb_si),
.scanb_so (scanb_so),
.scanb_en (scanb_en)
`endif
);
`else // !ETH_VIRTUAL_SILICON_RAM
//
// Generic single-port synchronous RAM model
//
//
// Generic RAM's registers and wires
//
reg [31:0] mem [255:0]; // RAM content
wire [31:0] q; // RAM output
reg [7:0] raddr; // RAM read address
//
// Data output drivers
//
assign do = (oe & ce) ? q : {32{1'bz}};
//
// RAM read and write
//
// read operation
always@(posedge clk)
if (ce) // && !we)
raddr
assign #1 q = rst ? {32{1'b0}} : mem[raddr];
// write operation
always@(posedge clk)
if (ce && we)
mem[addr]
// Task prints range of memory
// *** Remember that tasks are non reentrant, don't call this task in parallel for multiple instantiations.
task print_ram;
input [7:0] start;
input [7:0] finish;
integer rnum;
begin
for (rnum=start;rnum $display("Addr %h = %h",rnum,mem[rnum]);
end
endtask
`endif // !ETH_VIRTUAL_SILICON_RAM
`endif // !ETH_XILINX_RAMB4
endmodule
