Verilog module containing a synthesizable CRC function // * polynomial: (0 1 8) // * data width: 8
资源简介:Verilog module containing a synthesizable CRC function // * polynomial: (0 1 8) // * data width: 8
上传时间: 2016-09-26
上传用户:lacsx
资源简介:Verilog Overview n Basic Structure of a Verilog Model n Components of a Verilog Module – Ports – Data Types – Assigning Values and Numbers – Operators – Behavioral Modeling • Continuous Assignments • Procedural Block...
上传时间: 2017-02-18
上传用户:xinyuzhiqiwuwu
资源简介:crc_table.c is for reset seed( 0000 ) crc_table_1.c is for reset seed( ffff) CRC16_D8_m.v is a verilog module of byte paralle crc. CRC16_D8_m_tb.v is the testbench file of above module.
上传时间: 2014-01-09
上传用户:181992417
资源简介:Use the verilog language write a MIPS CPU code, and have additional instruction, for example: selection sort instruction. The code has contain combination circuit and sequenial circuit. CPU have contain ALU, ADD, ALU_CONTROL, DATA_MEMORY,...
上传时间: 2014-01-17
上传用户:yyyyyyyyyy
资源简介:This program demonstrates some function approximation capabilities of a Radial Basis Function Network. The user supplies a set of training points which represent some "sample" points for some arbitrary curve. Next, the user specifies the n...
上传时间: 2014-01-01
上传用户:zjf3110
资源简介:A fast customizable function for locating and measuring the peaks in noisy time-series signals.
上传时间: 2013-12-19
上传用户:changeboy
资源简介:A fast customizable function for locating and measuring the peaks in noisy time-series signals. Adjustable parameters allow discrimination of "real" signal peaks from noise and background.
上传时间: 2015-08-10
上传用户:xhz1993
资源简介:A fast customizable function for locating and measuring the peaks in noisy time-series signals. Adjustable parameters allow discrimination of "real" signal peaks from noise and background. Determines the position, height, and width of each ...
上传时间: 2015-08-10
上传用户:invtnewer
资源简介:Reducer: Given a dataset and a file containing a reduct, this program outputs a new dataset containing only the attributes appearing in the reduct file.
上传时间: 2014-01-25
上传用户:牛津鞋
资源简介:* This a software code module for a time-of-day clock object. * The clock may be fixed 12-hour, fixed 24-hour, or dynamically * configurable between these two types. Clock data can be accessed * as a binary number representing the num...
上传时间: 2013-12-07
上传用户:llandlu