This Verilog HDL description implements a UART Version 1.1 : Original Creation 2.1 : added comments
资源简介:This Verilog HDL description implements a UART Version 1.1 : Original Creation 2.1 : added comments
上传时间: 2016-05-27
上传用户:1109003457
资源简介:This Verilog HDL description implements a UART.
上传时间: 2013-12-17
上传用户:wff
资源简介:Verilog HDL: Magnitude For a vector (a,b), the magnitude representation is the following: A common approach to implementing these arithmetic functions is to use the Coordinate Rotation Digital Computer (CORDIC) algorithm. The CORDIC ...
上传时间: 2013-12-24
上传用户:金宜
资源简介:This document is a simplified version of the original. This version is not required to be treated as confidential and Non Disclosure Agreement with neither the 3C LLC nor the SDA is required. Reproduction in whole or in part is prohibited...
上传时间: 2014-12-08
上传用户:zhangyi99104144
资源简介:USB2.0 IP核,ASIC,FPGA可用,Verilog HDL源代码
上传时间: 2022-06-25
上传用户:qingfengchizhu
资源简介:this is a verilog hdl language referance book , tell you the basic useage of this language.
上传时间: 2016-02-06
上传用户:日光微澜
资源简介:this a Uart source code using Verilog.
上传时间: 2016-05-19
上传用户:zsjzc
资源简介:this a book about the verilog-hdl design and circuit simulation and synthesize example
上传时间: 2016-11-03
上传用户:GavinNeko
资源简介:What is Verilog? ➥ Verilog HDL is a Hardware Description Language (HDL) ➥ Verilog HDL allows describe designs at a high level of abstraction as well as the lower implementation levels ➥ Primary use of HDLs is the simul...
上传时间: 2017-02-18
上传用户:kjl
资源简介:本文利用Verilog HDL 语言自顶向下的设计方法设计多功能数字钟,突出了其作为硬件描述语言的良好的可读性、可移植性和易理解等优点,并通过Altera QuartusⅡ 4.1 和ModelSim SE 6.0 完成综合、仿真。此程序通过下载到FPGA 芯片后,可应用于实际的数字钟显示中...
上传时间: 2013-11-10
上传用户:hz07104032