-
`include "eth_phy_defines.v"
`include "wb_model_defines.v"
`include "tb_eth_defines.v"
`include "eth_defines.v"
`include "timescale.v"
module tb_ethernet();
reg wb_clk;
re
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// Address of PHY device (LXT971A)
`define ETH_PHY_ADDR 5'h01
// LED/Configuration pins on PHY device - see the specification, page 26, table 8
// Initial set of bits 13, 12 and
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`include "timescale.v"
module eth_miim
(
Clk,
Reset,
Divider,
NoPre,
CtrlData,
Rgad,
Fiad,
WCtrlData,
RStat,
ScanStat,
Mdi,
Mdo,
MdoEn,
Mdc,
Busy
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`include "tb_eth_defines.v"
`include "timescale.v"
module eth_memory
(
wb_clk_i, wb_rst_i, wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i,
wb_stb_i, wb_ack_o, wb_err_o, wb_dat_o, wb_dat_i
);
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`include "eth_defines.v"
`include "timescale.v"
module eth_top
(
// WISHBONE common
wb_clk_i, wb_rst_i, wb_dat_i, wb_dat_o,
// WISHBONE slave
wb_adr_i, wb_sel_i, wb_we_i, wb_
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-
`include "timescale.v"
module eth_rxstatem (MRxClk, Reset, MRxDV, ByteCntEq0, ByteCntGreat2, Transmitting, MRxDEq5, MRxDEqD,
IFGCounterEq24, ByteCntMaxFrame, StateData,
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-
`include "timescale.v"
module eth_rxaddrcheck(MRxClk, Reset, RxData, Broadcast ,r_Bro ,r_Pro,
ByteCntEq2, ByteCntEq3, ByteCntEq4, ByteCntEq5,
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//`define ETH_BIST // Bist for usage with Virtual Silicon RAMS
// Ethernet implemented in Xilinx Chips
// `define ETH_FIFO_XILINX // Use Xilinx distributed r
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-
`include "timescale.v"
module eth_clockgen(Clk, Reset, Divider, MdcEn, MdcEn_n, Mdc);
parameter Tp=1;
input Clk; // Input clock (Host clock)
input Reset;
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-
`include "timescale.v"
module eth_txethmac (MTxClk, Reset, TxStartFrm, TxEndFrm, TxUnderRun, TxData, CarrierSense,
Collision, Pad, CrcEn, FullD, HugEn, DlyCrcEn, MinFL,
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