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Primitive 16

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  • This code converts a Galois Field array created usin GF(2^m) for a given primitive polynomial into a

    This code converts a Galois Field array created usin GF(2^m) for a given primitive polynomial into a decimal array that can be used within typical .m file coding.

    /dl/201818.html

    标签: polynomial primitive converts created

    上传时间: 2015-09-26

    上传用户:wang5829

  • Use a one-dimensional array of primitive type boolean to represent the seating chart of the plane.

    Use a one-dimensional array of primitive type boolean to represent the seating chart of the plane. Initialize all the elements of the array to false to indicate that all the seats are empty. As each seat is assigned, set the corresponding elements of the array to true to indicate that the seat is no ...

    /dl/427483.html

    标签: one-dimensional primitive represent the

    上传时间: 2013-12-22

    上传用户:zhichenglu

  • Verilog_HDL的基本语法详解(夏宇闻版)

            Verilog_HDL的基本语法详解(夏宇闻版):Verilog HDL是一种用于数字逻辑电路设计的语言。用Verilog HDL描述的电路设计就是该电路的Verilog HDL模型。Verilog HDL既是一种行为描述的语言也是一种结构描述的语言。这也就是说,既可以用电路的功能描述也可以用元器件和它们之 ...

    /dl/32314.html

    标签: Verilog_HDL

    上传时间: 2013-11-23

    上传用户:青春给了作业95

  • XAPP1065 - 利用Spartan-6 FPGA设计扩频时钟发生器

      Consumer display applications commonly use high-speed LVDS interfaces to transfer videodata. Spread-spectrum clocking can be used to address electromagnetic compatibility (EMC)issues within these consumer devices. This application note uses Spartan®-6 FPGAs togenerate spread-spectrum ...

    /dl/32595.html

    标签: Spartan XAPP 1065 FPGA

    上传时间: 2014-12-28

    上传用户:yan2267246

  • DS306-PPC405 Virtex-4 Wrapper

    The PPC405 Virtex-4 is a wrapper around the Virtex-4PowerPC™ 405 Processor Block primitive. For detailsregarding the PowerPC 405, see the PowerPC 405 ProcessorBlock Reference Guide.

    /dl/32606.html

    标签: Wrapper Virtex 306 405

    上传时间: 2014-12-05

    上传用户:flg0001

  • Verilog_HDL的基本语法详解(夏宇闻版)

            Verilog_HDL的基本语法详解(夏宇闻版):Verilog HDL是一种用于数字逻辑电路设计的语言。用Verilog HDL描述的电路设计就是该电路的Verilog HDL模型。Verilog HDL既是一种行为描述的语言也是一种结构描述的语言。这也就是说,既可以用电路的功能描述也可以用元器件和它们之 ...

    /dl/39407.html

    标签: Verilog_HDL

    上传时间: 2014-12-04

    上传用户:cppersonal

  • DS306-PPC405 Virtex-4 Wrapper

    The PPC405 Virtex-4 is a wrapper around the Virtex-4PowerPC™ 405 Processor Block primitive. For detailsregarding the PowerPC 405, see the PowerPC 405 ProcessorBlock Reference Guide.

    /dl/40087.html

    标签: Wrapper Virtex 306 405

    上传时间: 2015-01-02

    上传用户:JIUSHICHEN

  • XAPP1065 - 利用Spartan-6 FPGA设计扩频时钟发生器

      Consumer display applications commonly use high-speed LVDS interfaces to transfer videodata. Spread-spectrum clocking can be used to address electromagnetic compatibility (EMC)issues within these consumer devices. This application note uses Spartan®-6 FPGAs togenerate spread-spectrum ...

    /dl/40096.html

    标签: Spartan XAPP 1065 FPGA

    上传时间: 2013-11-01

    上传用户:hjkhjk

  • Hard-decision decoding scheme Codeword length (n) : 31 symbols. Message length (k) : 19 symbols.

    Hard-decision decoding scheme Codeword length (n) : 31 symbols. Message length (k) : 19 symbols. Error correction capability (t) : 6 symbols One symbol represents 5 bit. Uses GF(2^5) with primitive polynomial p(x) = X^5 X^2 + 1 Generator polynomial, g(x) = a^15 a^21*X + a^6*X^2 + a^15*X^3 + a^ ...

    /dl/193880.html

    标签: symbols length Hard-decision Codeword

    上传时间: 2014-07-08

    上传用户:曹云鹏

  • The main purpose of this project is to add a new scheduling algorithm to GeekOS and to implement a s

    The main purpose of this project is to add a new scheduling algorithm to GeekOS and to implement a simple synchronization primitive (semaphore). As you might have already noticed, GeekOS uses a simple priority based preemptive Round Robin algorithm. In this project, you will change this to a multile ...

    /dl/273303.html

    标签: scheduling algorithm implement to

    上传时间: 2013-11-27

    上传用户:Late_Li