@TM:1141840652
@W: MT118 :"":0:0:0:-1|Paths from clock (top|CS_:f) to clock (top|OE_:r) are overconstrained because the required time of 0.01 ns is too small.
@N: MT195 :"":0:0:0:-1|This timing re
Selecting top level module top
@N:"C:\prj\Example-4-21\oe_edge\decode.v":3:7:3:12|Synthesizing module decode
@W: CL118 :"C:\prj\Example-4-21\oe_edge\decode.v":17:2:17:3|Latch generated from always
Selecting top level module top
@N:"C:\prj\Example-4-21\syn_wr\decode.v":3:7:3:12|Synthesizing module decode
@W: CL118 :"C:\prj\Example-4-21\syn_wr\decode.v":17:2:17:3|Latch generated from always b
